Tuyển dụng Applications Engineering, Sr Staff Engineer - STA

We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
Are you passionate about solving the toughest timing constraints and timing challenges ? Join Synopsys’
Signoff Static Timing Analysis (STA) team and work with industry-leading tools like
PrimeTime, enabling the world’s most advanced semiconductor designs.
In this customer-facing role, you will act as a technical expert in timing constraints (end to end) , timing signoff, timing ECO collaborating with semiconductor companies to support Synopsys industry-leading PrimeTime signoff solutions for advanced node designs.
You will work closely with customers, R&D, and product engineering teams to address complex timing challenges and drive methodology adoption.
This is a high-visibility, customer-facing role requiring strong technical depth, execution ownership, and cross-functional collaboration with Product and R&D teams.
What You'll Be Doing
Work with the leading semiconductor companies to solve complex timing constraints related issues
Provide expert guidance in timing constraints end to end and also work on the timing closure flow
Debug critical timing issues (lint , promote, demote, block2top , setup/hold, clocking, SI, variability)
Drive adoption of PrimeTime latest technologies and signoff flows
Work with R&D/product teams to resolve issues and drive enhancements
Develop reference flows, automation scripts (Tcl/Python), and best practices
Deliver technical training, workshops, and demos to customers
The Impact You Will Have
Strong hands-on expertise with
Synopsys PrimeTime
/ TCM
(or equivalent STA / Constraints tools)
Deep understanding of:
Timing constraints (SDC) end to end
Timing closure challenges
Strong debugging and problem-solving skills
Proficiency in
Tcl scripting
(Python/Perl is a plus)
Excellent communication and customer engagement skills
What You'll Need
B.Tech in Electronics and Communication Or M.Tech in VLSI/Embedded systems/Communication Systems.
Deep hands-on expertise with Synopsys PrimeTime, TCM, or equivalent static timing analysis and constraints tools in production design environments
Strong command of timing constraints end to end, including SDC creation, validation, and debugging across complex hierarchical designs
Excellent communication skills with demonstrated ability to engage customers, explain technical tradeoffs, and drive issues to resolution
Experience with RTL-based flows, mode merge, correlation, or high-performance designs like CPU, GPU, or AI/ML chips is beneficial
Who You Are
Experience with RTL based flow
Knowledge of Mode merge and correlation
Exposure to high-performance designs (CPU, GPU, AI/ML chips)
Prior customer-facing / application engineering experience
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.