Tuyển dụng ASIC Digital Design, Principal Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent a decade or more designing digital logic that has to hold up in real silicon, not just pass simulation, and you know that the difference between a block that tapes out clean and one that comes back with a respin is usually a micro-architecture decision made six months earlier. High-speed communication protocols are your territory. You have worked on DDR, HBM, or similar interfaces enough times to know where the edge cases live and how to design around them without overbuilding.

You think in trade-offs. Performance, power, area, latency and timing are not separate problems to you, they are variables in the same equation, and you know how to tune them for the market you are targeting. When a circuit team hands you, specifications or timing constraints that do not quite line up, you do not escalate immediately. You ask the right questions, model the scenarios, and figure out what actually needs to change.

Mentorship matters to you. You have seen engineers grow from writing their first FSM to owning entire subsystems, and you take that progression seriously. At Synopsys, you will work on next-generation memory and compute IP for high-performance computing, and the blocks you define will ship in products that power data centers and AI infrastructure.

What You'll Be Doing

Define micro-architecture for mixed-signal IP blocks from industry specifications and internal architecture definitions, balancing performance, power, area, latency and timing for HPC applications

Develop RTL for complex digital blocks within high-speed communication IP, including DDR and HBM interfaces

Model circuit behavior for analog and mixed-signal components to enable co-design and early validation

Define and refine synthesis constraints, working closely with physical design and timing closure teams to ensure your blocks meet targets

Run and review code quality checks (Lint, CDC and RDC analysis), catching issues early in the development cycle

Evaluate design trade-offs across multiple dimensions and recommend solutions that align with product goals and market requirements

Mentor engineers on your team, reviewing designs, providing technical guidance, and helping them build the judgment that comes with experience

This position could be performance in Lisbon and Porto.

The Impact You Will Have

Your micro-architecture decisions will define the performance and efficiency profile of next-generation memory IP used in high-performance computing systems

The RTL you develop will be synthesized, verified, and manufactured in leading-edge process nodes, directly affecting product competitiveness

Your behavioral models will enable early co-design between digital and analog teams, reducing integration risk and schedule slip

The constraints and design practices you establish will set the quality bar for the broader IP development team

Your mentorship will accelerate the growth of engineers around you, building the technical depth the team needs to scale

The trade-off analysis you provide will inform product roadmap decisions and help leadership prioritize the right features for the right markets

Your attention to CDC, RDC, and code quality will reduce downstream debug time and improve first-pass silicon success rates

What You'll Need

Master's degree in Electrical Engineering, Computer Engineering, or a related field

10+ years of hands-on ASIC digital design experience, with a strong track record of blocks that have taped out and worked

Deep expertise in high-speed communication protocols, specifically DDR, HBM, or similar memory interfaces

Solid understanding of low power design techniques and how to apply them in performance-critical contexts

Strong knowledge of clock domain crossing (CDC) and reset domain crossing (RDC) analysis, and experience resolving violations in complex designs

Experience with synthesis flows, including physical-aware synthesis and constraint definition for timing closure

Familiarity with mixed-signal design environments and the ability to work effectively with circuit designers and behavioral models is a strong plus

Who You Are

You can walk into a room with architects, analog designers, and verification engineers, listen to three conflicting constraints, and walk out with a design approach that actually works for all of them

When you review RTL, you do not just check for syntax. You are looking at the structure, the reusability, the assumptions baked into the logic, and whether it will hold up under corner cases

You are process-oriented in the best sense. When something breaks, you want to know why it broke and what upstream decision allowed it to happen, not just how to patch it

Detail matters to you. You catch the subtle bugs, the edge cases in the spec, the constraint that is slightly off, because you know those are the things that cost weeks in the lab later

You are comfortable navigating a multi-team environment where your block touches verification, physical design, circuit design, and system architecture, and you know how to keep all those threads aligned without losing momentum

You take mentorship seriously. You make time to review a junior engineer's design, explain why a different approach might scale better, and help them build the instincts that only come from doing the work

The Team You'll Be Part Of

You will be part of a multi-discipline product development team working on next-generation IP for high-performance computing. The work spans digital design, mixed-signal integration, verification, and physical implementation, and you will collaborate across all of those functions. The team is solving complex engineering challenges at the intersection of performance, power, and manufacturability, and the products you help build will be used in data centers and AI systems worldwide.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.